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ADC1061 10-Bit High-Speed P-Compatible A/D Converter with Track/Hold Function
June 1999
ADC1061 10-Bit High-Speed P-Compatible A/D Converter with Track/Hold Function
General Description
Using a modified half-flash conversion technique, the 10-bit ADC1061 CMOS analog-to-digital converter offers very fast conversion times yet dissipates a maximum of only 235 mW. The ADC1061 performs a 10-bit conversion in two lower-resolution "flashes", thus yielding a fast A/D without the cost, power dissipation, and other problems associated with true flash approaches. The analog input voltage to the ADC1061 is tracked and held by an internal sampling circuit. Input signals at frequencies from DC to greater than 160 kHz can therefore be digitized accurately without the need for an external sample-and-hold circuit. For ease of interface to microprocessors, the ADC1061 has been designed to appear as a memory location or I/O port without the need for external interface logic.
Features
n n n n n n 1.8 s maximum conversion time to 10 bits Low power dissipation: 235 mW (maximum) Built-in track-and-hold No external clock required Single +5V supply No missing codes over temperature
Applications
n n n n Waveform digitizers Disk drives Digital signal processor front ends Mobile telecommunications
Simplified Block and Connection Diagrams
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TRI-STATE (R) is a registered trademark of National Semiconductor Corporation.
(c) 1999 National Semiconductor Corporation
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Simplified Block and Connection Diagrams
(Continued)
Dual-In-Line Package
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Top View Order Number ADC1061CIN or ADC1061CIWM See NS Package J20A, M20B or N20A
Ordering Information
Industrial (-40C TA 85C) ADC1061CIN ADC1061CIWM Package N20A M20B
Pin Descriptions
Symbol DVCC, AVCC (1, 6) INT (2) S /H (3) RD (4) Function These are the digital and analog positive supply voltage inputs. They should always be connected to the same voltage source, but are brought out separately to allow for separate bypass capacitors. Each supply pin should be bypassed with a 0.1 F ceramic capacitor in parallel with a 10 F tantalum capacitor. This is the active low interrupt output. INT goes low at the end of each conversion, and returns to a high state following the rising edge of RD . This is the Sample/Hold control input. When this pin is forced low, it causes the analog input signal to be sampled and initiates a new conversion. This is the active low Read control input. When this pin is low, any data present in the ADC1061's output registers will be placed on the data bus. In Mode 2, the Read signal must be low until INT goes low. Until INT goes low, the data at the output pins will be incorrect. This is the active low Chip Select control input. This pin enables the S /H and RD inputs. These are the reference voltage inputs. They may be placed at any voltage between GND - 50 mV and VCC + 50 mV, but VREF+ must be greater than VREF-. An input voltage equal to VREF- produces an output code of 0, and an input voltage equal to VREF+ - 1LSB produces an output code of 1023. This is the analog input pin. The impedance of the source should be less than 500 for best accuracy and conversion speed. To avoid damage to the ADC1061, VIN should not be allowed to extend beyond the power supply voltages by more than 300 mV unless the drive current is limited. For accurate conversions, VIN should not extend more than 50 mV beyond the supply voltages. This is the power supply ground pin. The ground pin should be connected to a "clean" ground reference point. These are the TRI-STATE output pins.
CS (5) VREF-, VREF+ (7, 9) VIN (8)
GND (10) DB0-DB9 (11-20)
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ = AVCC = DVCC) Voltage at any Input or Output Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) ESD Susceptibility (Note 5) Soldering Information (Note 6) N Package (10 seconds) -0.3V to +6V -0.3V to V+ +0.3V 5 mA 20 mA 875 mW 1500V 260C
J Package (10 seconds) SO Package (Note 6) Vapor Phase (60 seconds) Infrared (15 seconds) Junction Temperature, TJ Storage Temperature Range
300C 215C 220C +150C -65C to +150C (Notes 1, 2) TMIN TA TMAX -40C TA +85C 4.5V to 5.5V
Operating Ratings
Temperature Range ADC1061CIN, ADC1061CIWM Supply Voltage Range
Converter Characteristics
The following specifications apply for V+ = +5V, VREF(+) = 5V, and VREF(-) = GND unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C. Symbol Resolution Total Unadjusted Error Integral Linearity Error Differential Linearity Error Offset Error Fullscale Error RREF RREF VREF(+) VREF(-) VREF(+) VREF(-) VIN VIN Reference Resistance Reference Resistance VREF(+) Input Voltage VREF(-) Input Voltage VREF(+) Input Voltage VREF(-) Input Voltage Input Voltage Input Voltage Analog Input Leakage Current Power Supply Sensitivity CS = V+, VIN = V+ CS = V+, VIN = GND V+ = 5V 5% VREF = 4.75V 0.01 0.01 Parameter Conditions Typical (Note 7) Limit (Note 8) 10 Units (Limit) Bits LSB (Max) LSB (Max) LSB (Max) LSB (Max) LSB (Max) k (Min) k (Max) V (Max) V (Min) V (Min) V (Max) V (Max) V (Min) A (Max) A (Max) LSB
1.0 0.3 0.1 0.5
0.65 0.65
2.0 1.5 1.0 1.0 1.0
0.4 0.9 V+ + 0.05 GND - 0.05 VREF(-) VREF(-) V+ + 0.05 GND - 0.05 3 -3
0.125
0.5
DC Electrical Characteristics
The following specifications apply for V+ = +5V, VREF(+) = 5V, and VREF(-) = GND unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C. Symbol VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) VOUT(0) IOUT DICC AICC Parameter Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current Logical "1" Output Voltage Logical "0" Output Voltage TRI-STATE (R) Output Current DVCC Supply Current AVCC Supply Current Conditions V+ = 5.25V V+ = 4.75V VIN(1) = 5V VIN(0) = 0V V+ = 4.75V IOUT = -360 A V+ = 4.75V IOUT = -10 A V+ = 4.75V IOUT = 1.6 mA VOUT = 5V VOUT = 0V CS = WR = RD = 0 CS = WR = RD = 0
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Typical (Note 7)
Limit (Note 8) 2.0 0.8
Units (Limits) V (Min) V (Max) A (Max) A (Max) V (Min) V (Min) V (Max) A (Max) A (Max) mA (Max) mA (Max)
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0.005 -0.005
1.0 -1.0 2.4 4.5 0.4
0.1 -0.1 0.1 30
50 -50 2 45
AC Electrical Characteristics
The following specifications apply for V+ = +5V, tr = tf = 20 ns, VREF(+) = 5V, and VREF(-) = GND unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C. Symbol tCONV tCRD tACC1 tACC2 tSH t1H, t0H tINTH tID tP SR CVIN COUT CIN Parameter Conversion Time from Rising Edge of S /H to Falling Edge of INT Conversion Time for MODE 2 (RD Mode) Access Time (Delay from Falling Edge of RD to Output Valid) Access Time (Delay from Falling Edge of RD to Output Valid) Minimum Sample Time TRI-STATE Control (Delay from Rising Edge of RD to High-Z State) Delay from Rising Edge of RD to Rising Edge of INT Delay from INT to Output Valid Delay from End of Conversion to Next Conversion Slew Rate for Correct Track-and-Hold Operation Analog Input Capacitance Logic Output Capacitance Logic Input Capacitance 35 5 5 pF pF pF 2.5 V/s CL = 100 pF 20 10 50 20 ns (Max) ns (Max) 10 50 ns (Max) (Figure 1); (Note 9) RL = 1k, CL = 10 pF 250 20 50 ns (Max) ns (Max) Mode 2; CL = 100 pF tCRD + 50 ns (Max) Mode 1; CL = 100 pF 20 50 ns (Max) Mode 2 1.8 2.4 s (Max) Conditions Mode 1 Typical (Note 7) 1.2 Limit (Note 8) 1.8 Units (Limits) s (Max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 150C, and the typical thermal resistance (JA) when board mounted is 47C/W for the plastic (N) package, 85C/W for the ceramic (J) package, and 65C/W for the small outline (WM) package. Note 5: Human body model, 100 pF discharged through a 1.5 k resistor. Note 6: See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" or the section titled "Surface Mount" found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: Typicals are at 25C and represent most likely parametric norm. Note 8: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 9: Accuracy may degrade if tSH is shorter than the value specified.
TRI-STATE Test Circuits and Waveforms
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TRI-STATE Test Circuits and Waveforms
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Timing Diagrams
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FIGURE 1. Mode 1. The conversion time (tCONV) is determined by the internal timer.
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FIGURE 2. Mode 2 (RD Mode). The conversion time (tCRD) includes the sampling time, and is determined by the internal timer.
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Typical Performance Characteristics
Zero (Offset) Error vs Reference Voltage Linearity Error vs Reference Voltage
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Mode 1 Conversion Time vs Temperature
Mode 2 Conversion Time vs Temperature
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Functional Description
The ADC1061 digitizes an analog input signal to 10 bits accuracy by performing two lower-resolution "flash" conversions. The first flash conversion provides the six most significant bits (MSBs) of data, and the second flash conversion provides the four least significant bits (LSBs).
Figure 3 is a simplified block diagram of the converter. Near the center of the diagram is a string of resistors. At the bottom of the string of resistors are 16 resistors, each of which has a value 1/1024th the resistance of the whole resistor string. These lower 16 resistors (the LSB Ladder) therefore have a voltage drop of 16/1024, or 1/64th of the total reference voltage (VREF+ - VREF-) across them. The remainder of the resistor string is made up of eight groups of eight resistors connected in series. These comprise the MSB Ladder. Each section of the MSB Ladder has 1/8th of the total reference voltage across it, and each of the MSB resistors has 1/64th of the total reference voltage across it. Tap points across all of these resistors can be connected, in groups, to the sixteen comparators at the right of the diagram. On the left side of the diagram is a string of seven resistors connected between VREF+ - VREF-. Six comparators compare the input voltage with the tap voltages on the resistor string to provide an estimate of the input voltage. This esti-
mate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the right. Note that the comparators on the left needn't be very accurate; they simply provide an estimate of the input voltage. Only the sixteen comparators on the right and the six on the left are necessary to perform the initial six-bit flash conversion, instead of the 64 comparators that would be required using conventional half-flash methods. To perform a conversion, the estimator compares the input voltage with the tap voltages on the seven resistors on the left. The estimator decoder then determines which MSB Ladder tap points will be connected to the sixteen comparators on the right. For example, assume that the estimator determines that VIN is between 11/16 and 13/16 of VREF. The estimator decoder will instruct the comparator mux to connect the 16 comparators to the taps on the MSB Ladder between 10/16 and 14/16 of VREF. The 16 comparators will then perform the first flash conversion. Note that since the comparators are connected to Ladder voltages that extend beyond the range indicated by the estimator circuit, errors in the estimator as large as 1/16 of the reference voltage (64 LSBs) will be corrected. This first flash conversion produces the six most significant bits of data.
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Functional Description
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FIGURE 3. Block Diagram of the Modified Half-Flash Converter Architecture The remaining four LSBs may now be determined using the same sixteen comparators that were used for the first flash conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted from the input voltage and compared with the tap points on the sixteen LSB Ladder resistors. The result of this second flash conversion is then decoded, and the full 10-bit result is latched. Note that the sixteen comparators used in the first flash conversion are reused for the second flash. Thus, the half-flash conversion techniques used in the ADC1061 needs only a small fraction of the number of comparators that would be required for a traditional flash converter, and far fewer than would be used in a conventional half-flash approach. This allows the ADC1061 to perform high-speed conversions without excessive power drain. tive. When S /H goes high, the result of the coarse conversion is latched and the "fine" conversion begins. After approximately 1.2 s (1.8 s maximum), INT goes low, indicating that the conversion results are latched and can be read by pulling RD low. Note that CS must be low to enable S /H or RD . CS is internally "ANDed" with the sample and read control signals; the input voltage is sampled when CS and S /H are low, and is read when CS and RD are low. MODE 2 In Mode 2, also called "RD mode", the S /H and RD pins are tied together. A conversion is initiated by pulling both pins low. The ADC1061 samples the input voltage and causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins the fine conversion. About 1.8 s (2.4 s maximum) after S /H and RD are pulled low, INT goes low, indicating that the conversion is complete. Approximately 20 ns later the data appearing on the TRI-STATE output pins will be valid. Note that data will appear on these pins throughout the conversion, but will be valid only after INT goes low.
Applications Information 1.0 Modes of Operation
The ADC1061 has two basic digital interface modes. These are illustrated in Figure 1 and Figure 2. MODE 1 In this mode, the S /H pin controls the start of conversion. S /H is pulled low for a minimum of 250 ns. This causes the comparators in the "coarse" flash converter to become ac-
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1.0 Modes of Operation
(Continued)
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FIGURE 4. Typical connection. Note the multiple bypass capacitors on the reference and power supply pins. If VREF- is not grounded, it should also be bypassed to ground using multiple capacitors (see 5.0 "Power Supply Considerations").
2.0 Reference Considerations
The ADC1061 has two reference inputs. These inputs, VREF+ and VREF-, are fully differential and define the zero to full-scale range of the input signal. The reference inputs can be connected to span the entire supply voltage range (VREF- = 0V, VREF+ = VCC) for ratiometric applications, or they can be connected to different voltages (as long as they are between ground and VCC) when other input spans are required. Reducing the overall VREF span to less than 5V increases the sensitivity of the converter (e.g., if VREF = 2V, then 1LSB = 1.953 mV). Note, however, that linearity and offset errors become larger when lower reference voltages are used. See the Typical Performance Curves for more information. Reference voltages less than 2V are not recommended. In most applications, VREF- will simply be connected to ground, but it is often useful to have an input span that is offset from ground. This situation is easily accommodated by the reference configuration used in the ADC1061. VREF- can be connected to a voltage other than ground as long as the reference for this pin is capable of sinking current. If VREF- is connected to a voltage other than ground, bypass it with multiple capacitors. Since the resistance between the two reference inputs can be as low as 400, the voltage source driving the reference inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors, so each of these pins must be supplied with a clean, low noise voltage source. Each reference pin should normally be bypassed with a 10 F tantalum and a 0.1 F ceramic capacitor. More bypassing may be necessary in some systems. The choice of reference voltage source will depend on the requirements of the system. In ratiometric data acquisition systems with a power supply-referenced sensor, the reference inputs are normally connected to VCC and GND, and no reference other than the power supply is necessary. In absolute measurement systems requiring 10-bit accuracy, a reference with better than 0.1% accuracy will be necessary.
3.0 The Analog Input
The ADC1061 samples the analog input voltage once every conversion cycle. When this happens, the input is briefly connected to an impedance approximately equal to 600 in series with 35 pF. Short-duration current spikes can therefore be observed at the analog input during normal operation. These spikes are normal and do not degrade the convertor's performance. Note that large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. Therefore, only signal sources with output impedances less than 500 should be used if rated accuracy is to be achieved at the minimum sample time. If the sampling time is increased, the source impedance can be larger. If a signal source has a high output impedance, its output should be buffered with an operational amplifier. The operational amplifier's output should be well-behaved when driving a switched 35 pF/600 load. Any ringing or voltage shifts at the op amp's output during the sampling period can result in conversion errors. Correct conversion results will be obtained for input voltages greater than GND - 50 mV and less than V+ + 50 mV. Do not allow the signal source to drive the analog input pin more than 300 mV higher than AVCC and DVCC, or more than 300 mV lower than GND. If the analog input pin is forced beyond these voltages, the current flowing through the pin should be limited to 5 mA or less to avoid permanent damage to the ADC1061.
4.0 Inherent Sample-and-Hold
Because the ADC1061 samples the input signal once during each conversion, it is capable of measuring relatively fast input signals without the help of an external sample-hold. In a conventional successive-approximation A/D converter, regardless of speed, the input signal must be stable to better than 12 LSB during each conversion cycle or significant errors will result. Consequently, even for many relatively slow input signals, the signals must be externally sampled and held constant during each conversion.
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4.0 Inherent Sample-and-Hold
(Continued) The ADC1061 can perform accurate conversions of input signals at frequencies from DC to greater than 160 kHz without the need for external sampling circuitry.
tiple power supplies, this may require careful attention to power supply sequencing. The ADC1061's power supply pins should be at the proper voltage before signals are applied to any of the other pins.
6.0 Layout and Grounding
In order to ensure fast, accurate conversions from the ADC1061, it is necessary to use appropriate circuit board layout techniques. The analog ground return path should be low-impedance and free of noise from other parts of the system. Noise from digital circuitry can be especially troublesome, so digital grounds should always be separate from analog grounds. For best performance, separate ground planes should be provided for the digital and analog parts of the system. All bypass capacitors should be located as close to the converter as possible and should connect to the converter and to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a filter capacitor) connected across the converter's input should be connected to a very clean ground return point. Grounding the component at the wrong point will result in reduced conversion accuracy.
5.0 Power Supply Considerations
The ADC1061 is designed to operate from a +5V (nominal) power supply. There are two supply pins, AVCC and DVCC. These pins allow separate external bypass capacitors for the analog and digital portions of the circuit. To guarantee accurate conversions, the two supply pins should be connected to the same voltage source, and each should be bypassed with a 0.1 F ceramic capacitor in parallel with a 10 F tantalum capacitor. Depending on the circuit board layout and other system considerations, more bypassing may be necessary. It is important to ensure that none of the ADC1061's input or output pins are ever driven to a voltage more than 300 mV above AVCC and DVCC, or more than 300 mV below GND. If these voltage limits are exceeded, the overdrive current into or out of any pin on the ADC1061 must be limited to less than 5 mA, and no more than 20 mA of overdrive current (all overdriven pins combined) should flow. In systems with mul-
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Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number ADC1061CIWM NS Package Number M20B
Order Number ADC1061CIN NS Package Number N20A
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ADC1061 10-Bit High-Speed P-Compatible A/D Converter with Track/Hold Function
Notes
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